How to use the Cache Mapping Calculator
- 1. Enter the sizesGive main memory, cache and block sizes with units, and pick the mapping.
- 2. Add an address or traceOptionally type a hex address to split, or a block number sequence to simulate.
- 3. Read the resultSee the formulas, tag/index/offset bits, tag directory size and a hit or miss for each access.
How cache mapping splits an address
A byte address is split into fields. The offset picks a byte inside a block, so offset bits = log2(block size). The index (line number for direct mapping, set number for set-associative) picks where the block can go. The tag is the rest and tells which memory block is stored there.
- Cache lines = cache size ÷ block size.
- Sets = lines ÷ k for a k-way set-associative cache. Direct mapped is 1-way. Fully associative is a single set.
- Index bits = log2(sets). Tag bits = address bits − index bits − offset bits.
- Tag directory size = lines × (tag bits + valid, dirty and other bits).
Worked example
Main memory is 4 GB, so the address has 32 bits. The cache is 64 KB with 64-byte blocks, so it has 64 KB ÷ 64 B = 1,024 lines. Offset = log264 = 6 bits.
- Direct mapped: line bits = log21024 = 10 and tag = 32 − 10 − 6 = 16. With one valid bit, the tag directory is 1,024 × 17 = 17,408 bits.
- 4-way set associative: 256 sets, so 8 set bits and an 18-bit tag.
- Fully associative: no index bits, so the tag is 26 bits.
Note that more ways means a longer tag and bigger comparators, but fewer conflict misses.
Simulating hits and misses
For a sequence of block numbers, the set is block mod number of sets. Take a 4-block cache and the sequence 0, 8, 0, 6, 8. Direct mapped gives 5 misses, because 0, 8 and 6 all map to line 0. A 2-way LRU cache gives 4 misses. Fully associative gives 3, which are only the compulsory misses. This is the classic Hennessy and Patterson example. To practise LRU on its own, try the LRU cache visualizer or the page replacement simulator.
Frequently asked questions
Is memory assumed to be byte-addressable?
Yes. For a word-addressable question, enter all sizes in words. The bit counts then come out in words.
What extra bits go into the tag directory?
Usually one valid bit, plus a dirty bit for write-back caches, and LRU bits for some set-associative caches. Enter the total extra bits per line.
Why must sizes be powers of 2?
Address fields are whole bits, so cache, block and memory sizes in exam problems are powers of 2.
What is the difference between a line and a block?
A block is a fixed-size chunk of main memory. A line is a slot in the cache that holds one block, plus its tag and status bits.